The present invention relates to integrated circuits, and more particularly to memories.
FIG. 1 illustrates a prior art DRAM (dynamic random access memory). Memory array 110 has DRAM memory cells arranged in rows and columns. Each cell has a capacitor and an access transistor connected in series. Each memory row corresponds to a wordline WL. To read the memory, the corresponding wordline WL is activated, and the data signals for the corresponding row appear on bitlines BL. The bitline signals are amplified by sense amplifiers (not shown). Y select circuit 130 selects one or more memory columns and couples the corresponding bitlines to a data path leading to a memory output terminal DQ. In a write operation, a reverse data path is provided from terminal DQ to the memory array.
To increase memory bandwidth, multiple data items can be prefetched in parallel from memory array 110 for a serial output on the DQ terminal. For example, in DDR (double date rate) synchronous DRAMS, two data bits are prefetched in parallel for sequential output on the rising and falling edges of a clock signal in a burst read operation (one bit is provided on terminal DQ on the rising edge, the other bit on the falling edge). Likewise, in a burst write operation, two data bits are received serially at the terminal DQ on the rising and falling edges of a clock cycle, and written to array 110 in parallel.
The parallel-to-serial and serial-to-parallel conversion of data within the memory is complicated by the requirement to provide different data ordering schemes in the DDR and some other kinds of memories. The DDR standard defines the following data sequences for the burst read and write operations (see JEDEC Standard JESD79D, JEDEC Solid State Technology Association, January 2004, incorporated herein by reference):
TABLE 1DDR BURST OPERATIONSData Sequence (i.e. AddressStarting CLSequence) within the BurstBurst LengthAddressInterleavedSequentialA0200-10-111-01-0A1 A04000-1-2-30-1-2-3011-0-3-21-2-3-0102-3-0-12-3-0-1113-2-1-03-0-1-2A2 A1 A080000-1-2-3-4-5-6-70-1-2-3-4-5-6-70011-0-3-2-5-4-7-61-2-3-4-5-6-7-00102-3-0-1-6-7-4-52-3-4-5-6-7-0-10113-2-1-0-7-6-5-43-4-5-6-7-0-1-21004-5-6-7-0-1-2-34-5-6-7-0-1-2-31015-4-7-6-1-0-3-25-6-7-0-1-2-3-41106-7-4-5-2-3-0-16-7-0-1-2-3-4-51117-6-5-4-3-2-1-07-0-1-2-3-4-5-6
Here A2, A1, A0 are the three least significant bits (LSB) of a burst operation's “starting address” An . . . A2A1A0 (or A<n:0>). For each burst length (2, 4, or 8), and each starting address, the DDR standard defines a sequential type ordering and an interleaved type ordering. The burst length and type are written to the memory mode register (not shown) before the burst begins. The data are read from, or written to, a block of 2, 4, or 8 memory locations. The block address is defined by the most significant address bits (bits A<n:3> for burst length of 8, bits A<n:2> for burst length of 4, bits A<n:1> for burst length of 2). The least significant address bits and the burst type define the data ordering within the block. For example, for the burst length of 4, the starting address A<n:0>=x . . . x01, and the interleaved type, the data are read or written at a block of four memory locations at addresses x . . . x00 through x . . . x11 in the order 1-0-3-2 (Table 1), i.e. the first data item is written to address x . . . x01, the second data item to address x . . . x00, the third data item to address x . . . x11, and the fourth data item to address x . . . x10 (the data ordering is the order of the address LSB's).
FIG. 1 illustrates a write data path for a DDR memory with a two bit prefetch as described in U.S. Pat. No. 6,621,747 issued Sep. 16, 2003 to Faue. Serial to parallel converter 132 performs a serial to parallel conversion on each pair of serial data bits received in a clock cycle on terminal DQ. Converter 132 drives a line IR with the first of the two bits (the bit received on the rising edge of the clock cycle), and drives another line IF with the second bit, received on the falling edge of the clock cycle. Lines IR, IF are shown at 138. Write data sort circuit 140 (WDSORT) re-orders the bits and drives a line G0 with the bit to be written to a memory location with A0=0, and the line G1 with the bit to be written to a location with A0=1. Lines G0, G1 are shown at 134. Y select circuit 130 selects the appropriate memory columns to write the two bits in parallel from lines 134 to their respective memory locations.
U.S. Pat. No. 6,115,321 (issued Sep. 5, 2000 to Koelling et al) describes a memory with a four bit prefetch. There are four lines 134 and four lines 138. Sorting circuit 140 is used for both the read and the write accesses. The proper data ordering for Table 1 is achieved via a cooperative operation of circuit 140 and Y select circuit 130.
U.S. Pat. No. 6,600,691 (issued Jul. 29, 2003 to Morzano et al) describes a read data path that can be used for a DDR2 memory. DDR2 is defined in JDEC standard JESD79-2A (JEDEC Solid State Technology Association, January 2004) incorporated herein by reference. The DDR2 standard specifies a double data rate memory (one data item on each clock cycle edge) with a four bit prefetch with the following burst data sequences:
TABLE 2DDR2 BURST OPERATIONSData Sequence (i.e. AddressStarting CLSequence) within the BurstBurst LengthAddressInterleavedSequentialA1 A04000-1-2-30-1-2-3011-0-3-21-2-3-0102-3-0-12-3-0-1113-2-1-03-0-1-2A2 A1 A080000-1-2-3-4-5-6-70-1-2-3-4-5-6-70011-0-3-2-5-4-7-61-2-3-0-5-6-7-40102-3-0-1-6-7-4-52-3-0-1-6-7-4-50113-2-1-0-7-6-5-43-0-1-2-7-4-5-61004-5-6-7-0-1-2-34-5-6-7-0-1-2-31015-4-7-6-1-0-3-25-6-7-4-1-2-3-01106-7-4-5-2-3-0-16-7-4-5-2-3-0-11117-6-5-4-3-2-1-07-4-5-6-3-0-1-2
Improved burst operation circuitry for DDR, DDR2, desirable.